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git.remi.lu Git - yamcumobo/.git/log
Rémi ESSAISSI [Wed, 27 Aug 2025 12:12:54 +0000 (12:12 +0000)]
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Rémi ESSAISSI [Wed, 27 Aug 2025 12:10:29 +0000 (12:10 +0000)]
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Rémi ESSAISSI [Wed, 27 Aug 2025 12:09:56 +0000 (12:09 +0000)]
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Rémi ESSAISSI [Wed, 27 Aug 2025 12:09:39 +0000 (12:09 +0000)]
back traces are wires !!
Rémi ESSAISSI [Wed, 27 Aug 2025 12:08:49 +0000 (12:08 +0000)]
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Rémi ESSAISSI [Wed, 27 Aug 2025 12:07:42 +0000 (12:07 +0000)]
zpill2 1.1 : added optional wires for SWD debug .
Rémi ESSAISSI [Wed, 27 Aug 2025 01:44:26 +0000 (01:44 +0000)]
still only one face PCB !!!
Rémi ESSAISSI [Wed, 27 Aug 2025 01:42:43 +0000 (01:42 +0000)]
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Rémi ESSAISSI [Wed, 27 Aug 2025 01:42:25 +0000 (01:42 +0000)]
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Rémi ESSAISSI [Wed, 27 Aug 2025 01:42:07 +0000 (01:42 +0000)]
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Rémi ESSAISSI [Wed, 27 Aug 2025 01:40:08 +0000 (01:40 +0000)]
zpill2: STM32H523xx jtag, OCTOSPI for ext memomy and display, optional lowpower xtal
Rémi ESSAISSI [Tue, 26 Aug 2025 20:33:59 +0000 (20:33 +0000)]
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Rémi ESSAISSI [Sat, 23 Aug 2025 15:04:31 +0000 (15:04 +0000)]
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Rémi ESSAISSI [Sat, 23 Aug 2025 15:04:19 +0000 (15:04 +0000)]
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Rémi ESSAISSI [Sat, 23 Aug 2025 15:04:04 +0000 (15:04 +0000)]
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Rémi ESSAISSI [Sat, 23 Aug 2025 15:03:47 +0000 (15:03 +0000)]
second daughter-board, DB9 Serial for your PC terminal sofware or more !
Rémi ESSAISSI [Sat, 23 Aug 2025 13:45:56 +0000 (13:45 +0000)]
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Rémi ESSAISSI [Sat, 23 Aug 2025 13:45:39 +0000 (13:45 +0000)]
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Rémi ESSAISSI [Sat, 23 Aug 2025 13:45:20 +0000 (13:45 +0000)]
db1 plus: LEDS and a Switch
Rémi ESSAISSI [Fri, 22 Aug 2025 00:03:06 +0000 (00:03 +0000)]
the, idea really .
Rémi ESSAISSI [Thu, 21 Aug 2025 20:22:23 +0000 (20:22 +0000)]
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Rémi ESSAISSI [Thu, 21 Aug 2025 20:22:07 +0000 (20:22 +0000)]
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Rémi ESSAISSI [Thu, 21 Aug 2025 20:21:56 +0000 (20:21 +0000)]
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Rémi ESSAISSI [Thu, 21 Aug 2025 20:21:39 +0000 (20:21 +0000)]
a first doghterboard, to be put in parallel / "back-to-back" on a breadboard for example or pre-made PCBs.
Rémi ESSAISSI [Thu, 21 Aug 2025 15:42:23 +0000 (15:42 +0000)]
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Rémi ESSAISSI [Thu, 21 Aug 2025 15:41:13 +0000 (15:41 +0000)]
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Rémi ESSAISSI [Thu, 21 Aug 2025 12:24:33 +0000 (12:24 +0000)]
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Rémi ESSAISSI [Thu, 21 Aug 2025 12:24:22 +0000 (12:24 +0000)]
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Rémi ESSAISSI [Thu, 21 Aug 2025 12:19:06 +0000 (12:19 +0000)]
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Rémi ESSAISSI [Thu, 21 Aug 2025 11:29:37 +0000 (11:29 +0000)]
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Rémi ESSAISSI [Thu, 21 Aug 2025 11:29:25 +0000 (11:29 +0000)]
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Rémi ESSAISSI [Thu, 21 Aug 2025 11:29:12 +0000 (11:29 +0000)]
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Rémi ESSAISSI [Thu, 21 Aug 2025 11:13:10 +0000 (11:13 +0000)]
Replace zpill-1.1.1.1-B-noCMP.png
Rémi ESSAISSI [Thu, 21 Aug 2025 11:12:39 +0000 (11:12 +0000)]
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Rémi ESSAISSI [Thu, 21 Aug 2025 11:11:07 +0000 (11:11 +0000)]
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Rémi ESSAISSI [Thu, 21 Aug 2025 04:39:47 +0000 (04:39 +0000)]
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Rémi ESSAISSI [Thu, 21 Aug 2025 04:07:45 +0000 (04:07 +0000)]
Added RS232 indicator LED
Rémi ESSAISSI [Thu, 21 Aug 2025 04:07:22 +0000 (04:07 +0000)]
Added RS232 indicator LED
Rémi ESSAISSI [Thu, 21 Aug 2025 04:07:02 +0000 (04:07 +0000)]
Added RS232 indicator LED
Rémi ESSAISSI [Thu, 21 Aug 2025 01:13:42 +0000 (01:13 +0000)]
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Rémi ESSAISSI [Wed, 20 Aug 2025 22:15:35 +0000 (22:15 +0000)]
fix possible power filtering errors
Rémi ESSAISSI [Wed, 20 Aug 2025 22:15:17 +0000 (22:15 +0000)]
fix possible power filtering errors
Rémi ESSAISSI [Wed, 20 Aug 2025 22:15:01 +0000 (22:15 +0000)]
fix possible power filtering errors
Rémi ESSAISSI [Wed, 20 Aug 2025 22:13:44 +0000 (22:13 +0000)]
Delete zpill-1.1.1.1-A.zip
Rémi ESSAISSI [Wed, 20 Aug 2025 22:13:30 +0000 (22:13 +0000)]
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Rémi ESSAISSI [Wed, 20 Aug 2025 22:13:11 +0000 (22:13 +0000)]
Delete zpill-1.1.1.1-A-CMP.png
Rémi ESSAISSI [Wed, 20 Aug 2025 22:08:19 +0000 (22:08 +0000)]
fix possible power filtering errors
Rémi ESSAISSI [Wed, 20 Aug 2025 22:07:51 +0000 (22:07 +0000)]
fix possible power filtering errors
Rémi ESSAISSI [Wed, 20 Aug 2025 22:07:23 +0000 (22:07 +0000)]
fix possible power filtering errors
Rémi ESSAISSI [Wed, 20 Aug 2025 20:05:57 +0000 (20:05 +0000)]
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Rémi ESSAISSI [Wed, 20 Aug 2025 20:05:33 +0000 (20:05 +0000)]
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Rémi ESSAISSI [Wed, 20 Aug 2025 20:05:15 +0000 (20:05 +0000)]
add output PADs if no use of LEDs.
Rémi ESSAISSI [Wed, 20 Aug 2025 15:58:01 +0000 (15:58 +0000)]
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Rémi ESSAISSI [Tue, 19 Aug 2025 22:35:28 +0000 (22:35 +0000)]
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Rémi ESSAISSI [Tue, 19 Aug 2025 22:35:12 +0000 (22:35 +0000)]
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Rémi ESSAISSI [Tue, 19 Aug 2025 22:34:57 +0000 (22:34 +0000)]
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Rémi ESSAISSI [Tue, 19 Aug 2025 18:49:21 +0000 (18:49 +0000)]
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Rémi ESSAISSI [Tue, 19 Aug 2025 18:49:02 +0000 (18:49 +0000)]
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Rémi ESSAISSI [Tue, 19 Aug 2025 18:48:48 +0000 (18:48 +0000)]
added switch for security
Rémi ESSAISSI [Tue, 19 Aug 2025 18:32:45 +0000 (18:32 +0000)]
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Rémi ESSAISSI [Tue, 19 Aug 2025 18:32:29 +0000 (18:32 +0000)]
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Rémi ESSAISSI [Tue, 19 Aug 2025 18:32:13 +0000 (18:32 +0000)]
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Rémi ESSAISSI [Tue, 19 Aug 2025 18:29:39 +0000 (18:29 +0000)]
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Rémi ESSAISSI [Tue, 19 Aug 2025 18:29:22 +0000 (18:29 +0000)]
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Rémi ESSAISSI [Tue, 19 Aug 2025 18:28:45 +0000 (18:28 +0000)]
Added switch to short USB 1 and 4 , to feed RS232 5v from USB .
Rémi ESSAISSI [Tue, 19 Aug 2025 01:14:40 +0000 (01:14 +0000)]
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Rémi ESSAISSI [Tue, 19 Aug 2025 01:14:28 +0000 (01:14 +0000)]
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Rémi ESSAISSI [Tue, 19 Aug 2025 01:14:11 +0000 (01:14 +0000)]
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Rémi ESSAISSI [Mon, 18 Aug 2025 19:59:13 +0000 (19:59 +0000)]
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Rémi ESSAISSI [Mon, 18 Aug 2025 19:58:58 +0000 (19:58 +0000)]
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Rémi ESSAISSI [Mon, 18 Aug 2025 18:35:30 +0000 (18:35 +0000)]
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Rémi ESSAISSI [Mon, 18 Aug 2025 16:08:57 +0000 (16:08 +0000)]
pin 1 and 4 connected, to be tested
Rémi ESSAISSI [Mon, 18 Aug 2025 16:08:18 +0000 (16:08 +0000)]
pin4 to VCC (5v) maybe illegal , but may work
Rémi ESSAISSI [Sun, 17 Aug 2025 20:11:10 +0000 (20:11 +0000)]
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Rémi ESSAISSI [Sun, 17 Aug 2025 10:50:03 +0000 (10:50 +0000)]
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Rémi ESSAISSI [Sun, 17 Aug 2025 10:49:46 +0000 (10:49 +0000)]
i2c and rs232 monitoring with LEDs
Rémi ESSAISSI [Sun, 17 Aug 2025 02:10:09 +0000 (02:10 +0000)]
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Rémi ESSAISSI [Sun, 17 Aug 2025 02:09:44 +0000 (02:09 +0000)]
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Rémi ESSAISSI [Sat, 16 Aug 2025 21:19:00 +0000 (21:19 +0000)]
Serial/RS232 monitoring with 4 LEDs .
Rémi ESSAISSI [Sat, 16 Aug 2025 21:16:29 +0000 (21:16 +0000)]
RS232 monitoring: 4 LEDs
Rémi ESSAISSI [Sat, 16 Aug 2025 09:35:38 +0000 (09:35 +0000)]
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Rémi ESSAISSI [Sat, 16 Aug 2025 09:34:21 +0000 (09:34 +0000)]
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Rémi ESSAISSI [Fri, 15 Aug 2025 22:30:58 +0000 (22:30 +0000)]
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Rémi ESSAISSI [Fri, 15 Aug 2025 22:30:47 +0000 (22:30 +0000)]
Delete zpillSILX.png
Rémi ESSAISSI [Fri, 15 Aug 2025 22:30:22 +0000 (22:30 +0000)]
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Rémi ESSAISSI [Fri, 15 Aug 2025 22:29:50 +0000 (22:29 +0000)]
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Rémi ESSAISSI [Fri, 15 Aug 2025 19:58:21 +0000 (19:58 +0000)]
Edit README.md
Rémi ESSAISSI [Fri, 15 Aug 2025 19:54:47 +0000 (19:54 +0000)]
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Rémi ESSAISSI [Fri, 15 Aug 2025 19:52:25 +0000 (19:52 +0000)]
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Rémi ESSAISSI [Fri, 15 Aug 2025 19:52:05 +0000 (19:52 +0000)]
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Rémi ESSAISSI [Fri, 15 Aug 2025 19:51:39 +0000 (19:51 +0000)]
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Rémi ESSAISSI [Fri, 15 Aug 2025 19:51:09 +0000 (19:51 +0000)]
SIL-18 , ready for your breadboard !
Rémi ESSAISSI [Fri, 15 Aug 2025 10:54:16 +0000 (10:54 +0000)]
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Rémi ESSAISSI [Fri, 15 Aug 2025 10:41:17 +0000 (10:41 +0000)]
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Rémi ESSAISSI [Thu, 14 Aug 2025 23:34:34 +0000 (23:34 +0000)]
Zpill, errors in kicad can be ignored, it is the power bridges,
Rémi ESSAISSI [Thu, 14 Aug 2025 23:32:43 +0000 (23:32 +0000)]
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Rémi ESSAISSI [Thu, 14 Aug 2025 23:32:27 +0000 (23:32 +0000)]
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Rémi ESSAISSI [Thu, 14 Aug 2025 23:32:04 +0000 (23:32 +0000)]
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Rémi ESSAISSI [Thu, 14 Aug 2025 23:31:44 +0000 (23:31 +0000)]
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Rémi ESSAISSI [Wed, 13 Aug 2025 18:49:40 +0000 (18:49 +0000)]
first traces , one layer for now .
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